ZL9117M
C OUT = -----------------------------------------
8 × f SW × --------------
whether the data is set up for a block write. Undesirable results
may be observed if the device’s V DD supply drops below 3.0V
during this process.
I opp
V orip
2
(EQ. 4)
V orip
2 × I opp
V orip = I opp × ESR + -------------------------------------
I opp
8 × f
× C
I CINrms = I OUT × D × ( 1 – D )
TABLE 3. SNAPSHOT_CONTROL COMMAND
DATA
VALUE DESCRIPTION
1 Copies current SNAPSHOT values from Flash memory to
RAM for immediate access using SNAPSHOT command.
2 Writes current SNAPSHOT values to Flash memory. Only
available when device is disabled.
If the module experiences a fault and power is lost, the user can
extract the last SnapShot parameters stored during the fault by
writing a 1 to SNAPSHOT_CONTROL (transfers data from Flash
memory to RAM) and then issuing a SNAPSHOT command (reads
data from RAM via SMBus).
Non-Volatile Memory and Device Security
Features
The ZL9117M has internal non-volatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them.
During the initialization process, the ZL9117M checks for stored
values contained in its internal non-volatile memory. The
ZL9117M offers two internal memory storage units that are
accessible by the user as follows:
1. Default Store: The ZL9117M has a default configuration that is
stored in the default store in the controller. The module can be
restored to its default settings by issuing a
RESTORE_DEFAULT_ALL command over the SMBus.
2. User Store: The user can modify certain power supply settings
as described in this data sheet. The user stores their
configuration in the user store.
Please refer to Application Note AN2033 for details on how to set
specific security measures via the I 2 C/SMBus interface.
OUTPUT CAPACITOR SELECTION
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
output deviation during transient load steps (V osag ) and low
output voltage ripple (V orip ). However, capacitors with low ESR,
such as semi-stable (X5R and X7R) dielectric ceramic capacitors,
also have relatively low capacitance values. Many designs can
use a combination of high capacitance devices and low ESR
devices in parallel.
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
shown in Equations 4 and 5:
16
(EQ. 5)
ESR = ---------------------
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage
ripple can be calculated using Equation 6:
(EQ. 6)
sw out
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the V orip should
be less than the desired maximum output ripple.
Usually, at higher output voltages, inductor ripple current is very
high so it is recommend to use a combination of several ceramic
capacitor with low ESR bulk capacitors to ensure low output
ripple voltage and loop stability. Inadequate amount of
capacitance at the output can cause instability to the control
loop.
INPUT CAPACITOR
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
(I CINrms ) can be determined from Equation 7:
(EQ. 7)
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated at 1.2X the ripple current calculated above to
avoid overheating of the capacitors due to the high ripple current,
which can cause premature failure. Ceramic capacitors with X7R
or X5R dielectric with low ESR and 1.1X the maximum expected
input voltage are recommended.
Layout Guide
To achieve stable operation, low losses, and good thermal
performance some layout considerations are necessary.
? Establish a separate ground plane for SGND (pin 9) and PGND
(pin 10 and pin 16) and connect them at a single point as
shown in the Figure 19. CV25, CVR, RSA, and RVSET are
placed on the bottom layer and are connected to a single
SGND plane that is connected to the PGND at a single point.
This will help to block the high frequency noise from entering
to the controller via SGND.
? Place a high frequency ceramic capacitor between (1) VIN and
PGND (pin 16), (2) VOUT and PGND (pin 16) and (3) bypass
capacitors between VDRV, VDD, V25, VR and the ground plane,
as close to the module as possible to minimize high frequency
noise. High frequency ceramic capacitors close to the module
FN7914.3
July 22, 2013
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